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<ul>
<li><a href="#about" style=" font-size: 16px;">Synthesis Messages</a></li>
<li><a href="#summary" style=" font-size: 16px;">Synthesis Details</a></li>
<li><a href="#resource" style=" font-size: 16px;">Resource</a>
<ul>
<li><a href="#usage" style=" font-size: 14px;">Resource Usage Summary</a></li>
<li><a href="#utilization" style=" font-size: 14px;">Resource Utilization Summary</a></li>
</ul>
</li>
<li><a href="#timing" style=" font-size: 16px;">Timing</a>
<ul>
<li><a href="#clock" style=" font-size: 14px;">Clock Summary</a></li>
<li><a href="#performance" style=" font-size: 14px;">Max Frequency Summary</a></li>
<li><a href="#detail timing" style=" font-size: 14px;">Detail Timing Paths Informations</a></li>
</ul>
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<div id="content">
<h1><a name="about">Synthesis Messages</a></h1>
<table class="summary_table">
<tr>
<td class="label">Report Title</td>
<td>GowinSynthesis Report</td>
</tr>
<tr>
<td class="label">Design File</td>
<td>K:\downloads\Gowin_V1.9.11_x64_win\Gowin_V1.9.11_x64_win\Gowin_V1.9.11_x64\IDE\ipcore\RiscV_AE350_SOC\data\riscv_ae350_top.v<br>
K:\downloads\Gowin_V1.9.11_x64_win\Gowin_V1.9.11_x64_win\Gowin_V1.9.11_x64\IDE\ipcore\RiscV_AE350_SOC\data\riscv_ae350_soc.v<br>
K:\downloads\Gowin_V1.9.11_x64_win\Gowin_V1.9.11_x64_win\Gowin_V1.9.11_x64\IDE\ipcore\RiscV_AE350_SOC\data\riscv_ae350_ddr3.v<br>
K:\downloads\Gowin_V1.9.11_x64_win\Gowin_V1.9.11_x64_win\Gowin_V1.9.11_x64\IDE\ipcore\RiscV_AE350_SOC\data\riscv_ae350_flash.v<br>
K:\downloads\Gowin_V1.9.11_x64_win\Gowin_V1.9.11_x64_win\Gowin_V1.9.11_x64\IDE\ipcore\RiscV_AE350_SOC\data\ddr3_1_4code_hs.v<br>
K:\downloads\Gowin_V1.9.11_x64_win\Gowin_V1.9.11_x64_win\Gowin_V1.9.11_x64\IDE\ipcore\RiscV_AE350_SOC\data\DDR3_TOP.v<br>
K:\downloads\Gowin_V1.9.11_x64_win\Gowin_V1.9.11_x64_win\Gowin_V1.9.11_x64\IDE\ipcore\RiscV_AE350_SOC\data\fifo_top_32to128.v<br>
K:\downloads\Gowin_V1.9.11_x64_win\Gowin_V1.9.11_x64_win\Gowin_V1.9.11_x64\IDE\ipcore\RiscV_AE350_SOC\data\fifo_top_128to32.v<br>
K:\downloads\Gowin_V1.9.11_x64_win\Gowin_V1.9.11_x64_win\Gowin_V1.9.11_x64\IDE\ipcore\RiscV_AE350_SOC\data\gw_dtcm.v<br>
K:\downloads\Gowin_V1.9.11_x64_win\Gowin_V1.9.11_x64_win\Gowin_V1.9.11_x64\IDE\ipcore\RiscV_AE350_SOC\data\gw_itcm.v<br>
</td>
</tr>
<tr>
<td class="label">GowinSynthesis Constraints File</td>
<td>---</td>
</tr>
<tr>
<td class="label">Tool Version</td>
<td>V1.9.11 (64-bit)</td>
</tr>
<tr>
<td class="label">Part Number</td>
<td>GW5AST-LV138FPG676AES</td>
</tr>
<tr>
<td class="label">Device</td>
<td>GW5AST-138</td>
</tr>
<tr>
<td class="label">Device Version</td>
<td>B</td>
</tr>
<tr>
<td class="label">Created Time</td>
<td>Thu May  8 18:11:16 2025
</td>
</tr>
<tr>
<td class="label">Legal Announcement</td>
<td>Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved.</td>
</tr>
</table>
<h1><a name="summary">Synthesis Details</a></h1>
<table class="summary_table">
<tr>
<td class="label">Top Level Module</td>
<td>RiscV_AE350_SOC_Top</td>
</tr>
<tr>
<td class="label">Synthesis Process</td>
<td>Running parser:<br/>&nbsp;&nbsp;&nbsp;&nbsp;CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 99.219MB<br/>Running netlist conversion:<br/>&nbsp;&nbsp;&nbsp;&nbsp;CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.024s, Peak memory usage = 99.219MB<br/>Running device independent optimization:<br/>&nbsp;&nbsp;&nbsp;&nbsp;Optimizing Phase 0: CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.117s, Peak memory usage = 99.219MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Optimizing Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.021s, Peak memory usage = 99.219MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Optimizing Phase 2: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.089s, Peak memory usage = 99.219MB<br/>Running inference:<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 0: CPU time = 0h 0m 0.218s, Elapsed time = 0h 0m 0.21s, Peak memory usage = 99.219MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 1: CPU time = 0h 0m 0.312s, Elapsed time = 0h 0m 0.321s, Peak memory usage = 99.219MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 2: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.079s, Peak memory usage = 99.219MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 3: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.028s, Peak memory usage = 99.219MB<br/>Running technical mapping:<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 0: CPU time = 0h 0m 0.748s, Elapsed time = 0h 0m 0.744s, Peak memory usage = 99.219MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 1: CPU time = 0h 0m 0.577s, Elapsed time = 0h 0m 0.577s, Peak memory usage = 99.219MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 2: CPU time = 0h 0m 0.218s, Elapsed time = 0h 0m 0.218s, Peak memory usage = 99.219MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 3: CPU time = 0h 0m 4s, Elapsed time = 0h 0m 4s, Peak memory usage = 129.250MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 4: CPU time = 0h 0m 0.655s, Elapsed time = 0h 0m 0.823s, Peak memory usage = 129.250MB<br/>Generate output files:<br/>&nbsp;&nbsp;&nbsp;&nbsp;CPU time = 0h 0m 0.561s, Elapsed time = 0h 0m 0.641s, Peak memory usage = 156.367MB<br/></td>
</tr>
<tr>
<td class="label">Total Time and Memory Usage</td>
<td>CPU time = 0h 0m 8s, Elapsed time = 0h 0m 8s, Peak memory usage = 156.367MB</td>
</tr>
</table>
<h1><a name="resource">Resource</a></h1>
<h2><a name="usage">Resource Usage Summary</a></h2>
<table class="summary_table">
<tr>
<td class="label"><b>Resource</b></td>
<td><b>Usage</b></td>
</tr>
<tr>
<td class="label"><b>I/O Port </b></td>
<td>354</td>
</tr>
<tr>
<td class="label"><b>I/O Buf </b></td>
<td>354</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspIBUF</td>
<td>116</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspOBUF</td>
<td>194</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspIOBUF</td>
<td>44</td>
</tr>
<tr>
<td class="label"><b>Register </b></td>
<td>4323</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFFRE</td>
<td>4097</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFFPE</td>
<td>5</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFFCE</td>
<td>220</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDLCE</td>
<td>1</td>
</tr>
<tr>
<td class="label"><b>LUT </b></td>
<td>2777</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspLUT2</td>
<td>270</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspLUT3</td>
<td>132</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspLUT4</td>
<td>2375</td>
</tr>
<tr>
<td class="label"><b>ALU </b></td>
<td>55</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspALU</td>
<td>55</td>
</tr>
<tr>
<td class="label"><b>INV </b></td>
<td>102</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspINV</td>
<td>102</td>
</tr>
<tr>
<td class="label"><b>AE350_SOC </b></td>
<td>1</td>
</tr>
</table>
<h2><a name="utilization">Resource Utilization Summary</a></h2>
<table class="summary_table">
<tr>
<td class="label"><b>Resource</b></td>
<td><b>Usage</b></td>
<td><b>Utilization</b></td>
</tr>
<tr>
<td class="label">Logic</td>
<td>2934(2879 LUT, 55 ALU) / 138240</td>
<td>3%</td>
</tr>
<tr>
<td class="label">Register</td>
<td>4323 / 139140</td>
<td>4%</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp--Register as Latch</td>
<td>1 / 139140</td>
<td><1%</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp--Register as FF</td>
<td>4322 / 139140</td>
<td>4%</td>
</tr>
<tr>
<td class="label">BSRAM</td>
<td>0 / 340</td>
<td>0%</td>
</tr>
</table>
<h1><a name="timing">Timing</a></h1>
<h2><a name="clock">Clock Summary:</a></h2>
<table class="summary_table">
<tr>
<th>NO.</th>
<th>Clock Name</th>
<th>Type</th>
<th>Period</th>
<th>Frequency(MHz)</th>
<th>Rise</th>
<th>Fall</th>
<th>Source</th>
<th>Master</th>
<th>Object</th>
</tr>
<tr>
<td>1</td>
<td>AHB_CLK</td>
<td>Base</td>
<td>10.000</td>
<td>100.000</td>
<td>0.000</td>
<td>5.000</td>
<td> </td>
<td> </td>
<td>AHB_CLK_ibuf/I </td>
</tr>
<tr>
<td>2</td>
<td>FLASH_SPI_CLK_iobuf/I</td>
<td>Base</td>
<td>10.000</td>
<td>100.000</td>
<td>0.000</td>
<td>5.000</td>
<td> </td>
<td> </td>
<td>FLASH_SPI_CLK_iobuf/I </td>
</tr>
<tr>
<td>3</td>
<td>FLASH_SPI_CLK_in</td>
<td>Base</td>
<td>10.000</td>
<td>100.000</td>
<td>0.000</td>
<td>5.000</td>
<td> </td>
<td> </td>
<td>FLASH_SPI_CLK_iobuf/O </td>
</tr>
</table>
<h2><a name="performance">Max Frequency Summary:</a></h2>
<table class="summary_table">
<tr>
<th>NO.</th>
<th>Clock Name</th>
<th>Constraint</th>
<th>Actual Fmax</th>
<th>Logic Level</th>
<th>Entity</th>
</tr>
<tr>
<td>1</td>
<td>AHB_CLK</td>
<td>100.000(MHz)</td>
<td>77.912(MHz)</td>
<td>7</td>
<td>TOP</td>
</tr>
</table>
<h2><a name="detail timing">Detail Timing Paths Information</a></h2>
<h3>Path&nbsp1</h3>
<b>Path Summary:</b></br>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-1.417</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>6.794</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>5.376</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_cs_r_3_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/master_clk_d_en_r_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>AHB_CLK[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>AHB_CLK[R]</td>
</tr>
</table>
<b>Data Arrival Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>AHB_CLK</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>AHB_CLK_ibuf/I</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tINS</td>
<td>RR</td>
<td>4323</td>
<td>AHB_CLK_ibuf/O</td>
</tr>
<tr>
<td>0.413</td>
<td>0.413</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_cs_r_3_s0/CLK</td>
</tr>
<tr>
<td>0.795</td>
<td>0.382</td>
<td>tC2Q</td>
<td>RR</td>
<td>22</td>
<td>u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_cs_r_3_s0/Q</td>
</tr>
<tr>
<td>1.207</td>
<td>0.413</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n720_s4/I0</td>
</tr>
<tr>
<td>1.786</td>
<td>0.579</td>
<td>tINS</td>
<td>RR</td>
<td>8</td>
<td>u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n720_s4/F</td>
</tr>
<tr>
<td>2.199</td>
<td>0.413</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/rx_bit_cnt_r_4_s4/I2</td>
</tr>
<tr>
<td>2.706</td>
<td>0.507</td>
<td>tINS</td>
<td>RR</td>
<td>7</td>
<td>u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/rx_bit_cnt_r_4_s4/F</td>
</tr>
<tr>
<td>3.119</td>
<td>0.413</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/master_clk_en_s4/I0</td>
</tr>
<tr>
<td>3.698</td>
<td>0.579</td>
<td>tINS</td>
<td>RR</td>
<td>5</td>
<td>u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/master_clk_en_s4/F</td>
</tr>
<tr>
<td>4.110</td>
<td>0.413</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/spi_ns_1_s9/I3</td>
</tr>
<tr>
<td>4.399</td>
<td>0.289</td>
<td>tINS</td>
<td>RR</td>
<td>3</td>
<td>u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/spi_ns_1_s9/F</td>
</tr>
<tr>
<td>4.811</td>
<td>0.413</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/spi_ns_1_s8/I0</td>
</tr>
<tr>
<td>5.390</td>
<td>0.579</td>
<td>tINS</td>
<td>RR</td>
<td>3</td>
<td>u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/spi_ns_1_s8/F</td>
</tr>
<tr>
<td>5.803</td>
<td>0.413</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/master_clk_en_s1/I0</td>
</tr>
<tr>
<td>6.381</td>
<td>0.579</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/master_clk_en_s1/F</td>
</tr>
<tr>
<td>6.794</td>
<td>0.413</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/master_clk_d_en_r_s0/D</td>
</tr>
</table>
<b>Data Required Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>AHB_CLK</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>1</td>
<td>AHB_CLK_ibuf/I</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tINS</td>
<td>FF</td>
<td>4323</td>
<td>AHB_CLK_ibuf/O</td>
</tr>
<tr>
<td>5.385</td>
<td>0.385</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/master_clk_d_en_r_s0/CLK</td>
</tr>
<tr>
<td>5.376</td>
<td>-0.009</td>
<td>tSu</td>
<td> </td>
<td>1</td>
<td>u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/master_clk_d_en_r_s0</td>
</tr>
</table>
<b>Path Statistics:</b>
<table class="summary_table">
<tr>
<td class="label">Clock Skew:</td>
<td>-0.028</td>
</tr>
<tr>
<td class="label">Setup Relationship:</td>
<td>5.000</td>
</tr>
<tr>
<td class="label">Logic Level:</td>
<td>7</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay:</td><td> cell: 0.000, 0.000%; route: 0.413, 100.000%</td></tr>
<tr>
<td class="label">Arrival Data Path Delay:</td><td> cell: 3.111, 48.756%; route: 2.887, 45.250%; tC2Q: 0.382, 5.994%</td></tr>
<tr>
<td class="label">Required Clock Path Delay:</td><td> cell: 0.000, 0.000%; route: 0.413, 100.000%</td></tr>
</table>
<br/>
<h3>Path&nbsp2</h3>
<b>Path Summary:</b></br>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-1.543</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>11.891</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.349</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/clock_cnt_r_0_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_fifo/u_spi_txfifo/empty_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>AHB_CLK[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>AHB_CLK[R]</td>
</tr>
</table>
<b>Data Arrival Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>AHB_CLK</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>AHB_CLK_ibuf/I</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tINS</td>
<td>RR</td>
<td>4323</td>
<td>AHB_CLK_ibuf/O</td>
</tr>
<tr>
<td>0.413</td>
<td>0.413</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/clock_cnt_r_0_s1/CLK</td>
</tr>
<tr>
<td>0.795</td>
<td>0.382</td>
<td>tC2Q</td>
<td>RR</td>
<td>5</td>
<td>u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/clock_cnt_r_0_s1/Q</td>
</tr>
<tr>
<td>1.207</td>
<td>0.413</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/spi_ns_1_s11/I0</td>
</tr>
<tr>
<td>1.786</td>
<td>0.579</td>
<td>tINS</td>
<td>RR</td>
<td>3</td>
<td>u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/spi_ns_1_s11/F</td>
</tr>
<tr>
<td>2.199</td>
<td>0.413</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/rx_mask_cnt_r_1_s5/I0</td>
</tr>
<tr>
<td>2.778</td>
<td>0.579</td>
<td>tINS</td>
<td>RR</td>
<td>4</td>
<td>u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/rx_mask_cnt_r_1_s5/F</td>
</tr>
<tr>
<td>3.190</td>
<td>0.413</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/rx_mask_cnt_r_1_s4/I0</td>
</tr>
<tr>
<td>3.769</td>
<td>0.579</td>
<td>tINS</td>
<td>RR</td>
<td>8</td>
<td>u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/rx_mask_cnt_r_1_s4/F</td>
</tr>
<tr>
<td>4.181</td>
<td>0.413</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_1_s7/I0</td>
</tr>
<tr>
<td>4.760</td>
<td>0.579</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_1_s7/F</td>
</tr>
<tr>
<td>5.173</td>
<td>0.413</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_1_s3/I2</td>
</tr>
<tr>
<td>5.680</td>
<td>0.507</td>
<td>tINS</td>
<td>RR</td>
<td>3</td>
<td>u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_1_s3/F</td>
</tr>
<tr>
<td>6.093</td>
<td>0.413</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/arb_addr_latched_sclk_Z_s2/I0</td>
</tr>
<tr>
<td>6.671</td>
<td>0.579</td>
<td>tINS</td>
<td>RR</td>
<td>3</td>
<td>u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/arb_addr_latched_sclk_Z_s2/F</td>
</tr>
<tr>
<td>7.084</td>
<td>0.413</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_fifo/u_spi_txfifo/next_gray_rd_ptr_0_s3/I0</td>
</tr>
<tr>
<td>7.663</td>
<td>0.579</td>
<td>tINS</td>
<td>RR</td>
<td>14</td>
<td>u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_fifo/u_spi_txfifo/next_gray_rd_ptr_0_s3/F</td>
</tr>
<tr>
<td>8.075</td>
<td>0.413</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_fifo/u_spi_txfifo/next_bin_rd_ptr_6_s3/I2</td>
</tr>
<tr>
<td>8.583</td>
<td>0.507</td>
<td>tINS</td>
<td>RR</td>
<td>4</td>
<td>u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_fifo/u_spi_txfifo/next_bin_rd_ptr_6_s3/F</td>
</tr>
<tr>
<td>8.995</td>
<td>0.413</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_fifo/u_spi_txfifo/next_bin_rd_ptr_7_s4/I2</td>
</tr>
<tr>
<td>9.503</td>
<td>0.507</td>
<td>tINS</td>
<td>RR</td>
<td>2</td>
<td>u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_fifo/u_spi_txfifo/next_bin_rd_ptr_7_s4/F</td>
</tr>
<tr>
<td>9.915</td>
<td>0.413</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_fifo/u_spi_txfifo/next_gray_rd_ptr_6_s0/I1</td>
</tr>
<tr>
<td>10.515</td>
<td>0.600</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_fifo/u_spi_txfifo/next_gray_rd_ptr_6_s0/COUT</td>
</tr>
<tr>
<td>10.900</td>
<td>0.385</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_fifo/u_spi_txfifo/n465_s1/I0</td>
</tr>
<tr>
<td>11.479</td>
<td>0.579</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_fifo/u_spi_txfifo/n465_s1/F</td>
</tr>
<tr>
<td>11.891</td>
<td>0.413</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_fifo/u_spi_txfifo/empty_s0/D</td>
</tr>
</table>
<b>Data Required Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>AHB_CLK</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>AHB_CLK_ibuf/I</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tINS</td>
<td>RR</td>
<td>4323</td>
<td>AHB_CLK_ibuf/O</td>
</tr>
<tr>
<td>10.413</td>
<td>0.413</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_fifo/u_spi_txfifo/empty_s0/CLK</td>
</tr>
<tr>
<td>10.349</td>
<td>-0.064</td>
<td>tSu</td>
<td> </td>
<td>1</td>
<td>u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_fifo/u_spi_txfifo/empty_s0</td>
</tr>
</table>
<b>Path Statistics:</b>
<table class="summary_table">
<tr>
<td class="label">Clock Skew:</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship:</td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level:</td>
<td>12</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay:</td><td> cell: 0.000, 0.000%; route: 0.413, 100.000%</td></tr>
<tr>
<td class="label">Arrival Data Path Delay:</td><td> cell: 6.174, 53.784%; route: 4.922, 42.884%; tC2Q: 0.382, 3.332%</td></tr>
<tr>
<td class="label">Required Clock Path Delay:</td><td> cell: 0.000, 0.000%; route: 0.413, 100.000%</td></tr>
</table>
<br/>
<h3>Path&nbsp3</h3>
<b>Path Summary:</b></br>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-0.965</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>11.066</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.101</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_cs_r_1_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_8_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>AHB_CLK[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>AHB_CLK[R]</td>
</tr>
</table>
<b>Data Arrival Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>AHB_CLK</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>AHB_CLK_ibuf/I</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tINS</td>
<td>RR</td>
<td>4323</td>
<td>AHB_CLK_ibuf/O</td>
</tr>
<tr>
<td>0.413</td>
<td>0.413</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_cs_r_1_s0/CLK</td>
</tr>
<tr>
<td>0.795</td>
<td>0.382</td>
<td>tC2Q</td>
<td>RR</td>
<td>27</td>
<td>u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_cs_r_1_s0/Q</td>
</tr>
<tr>
<td>1.207</td>
<td>0.413</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/master_clk_en_s5/I0</td>
</tr>
<tr>
<td>1.786</td>
<td>0.579</td>
<td>tINS</td>
<td>RR</td>
<td>5</td>
<td>u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/master_clk_en_s5/F</td>
</tr>
<tr>
<td>2.199</td>
<td>0.413</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/spi_ns_1_s18/I0</td>
</tr>
<tr>
<td>2.778</td>
<td>0.579</td>
<td>tINS</td>
<td>RR</td>
<td>3</td>
<td>u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/spi_ns_1_s18/F</td>
</tr>
<tr>
<td>3.190</td>
<td>0.413</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/spi_ns_1_s10/I1</td>
</tr>
<tr>
<td>3.758</td>
<td>0.567</td>
<td>tINS</td>
<td>RR</td>
<td>4</td>
<td>u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/spi_ns_1_s10/F</td>
</tr>
<tr>
<td>4.170</td>
<td>0.413</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/n332_s1/I2</td>
</tr>
<tr>
<td>4.678</td>
<td>0.507</td>
<td>tINS</td>
<td>RR</td>
<td>14</td>
<td>u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/n332_s1/F</td>
</tr>
<tr>
<td>5.090</td>
<td>0.413</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_0_s3/I0</td>
</tr>
<tr>
<td>5.669</td>
<td>0.579</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_0_s3/F</td>
</tr>
<tr>
<td>6.081</td>
<td>0.413</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_0_s2/I0</td>
</tr>
<tr>
<td>6.660</td>
<td>0.579</td>
<td>tINS</td>
<td>RR</td>
<td>6</td>
<td>u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_0_s2/F</td>
</tr>
<tr>
<td>7.073</td>
<td>0.413</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n9_s0/I1</td>
</tr>
<tr>
<td>7.673</td>
<td>0.600</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n9_s0/COUT</td>
</tr>
<tr>
<td>7.673</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n10_s0/CIN</td>
</tr>
<tr>
<td>7.723</td>
<td>0.050</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n10_s0/COUT</td>
</tr>
<tr>
<td>7.723</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n11_s0/CIN</td>
</tr>
<tr>
<td>7.773</td>
<td>0.050</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n11_s0/COUT</td>
</tr>
<tr>
<td>7.773</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n12_s0/CIN</td>
</tr>
<tr>
<td>7.823</td>
<td>0.050</td>
<td>tINS</td>
<td>RR</td>
<td>7</td>
<td>u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n12_s0/COUT</td>
</tr>
<tr>
<td>8.235</td>
<td>0.413</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/tx_bit_cnt_r_4_s6/I0</td>
</tr>
<tr>
<td>8.814</td>
<td>0.579</td>
<td>tINS</td>
<td>RR</td>
<td>8</td>
<td>u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/tx_bit_cnt_r_4_s6/F</td>
</tr>
<tr>
<td>9.226</td>
<td>0.413</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_8_s5/I2</td>
</tr>
<tr>
<td>9.734</td>
<td>0.507</td>
<td>tINS</td>
<td>RR</td>
<td>9</td>
<td>u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_8_s5/F</td>
</tr>
<tr>
<td>10.146</td>
<td>0.413</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_8_s3/I2</td>
</tr>
<tr>
<td>10.654</td>
<td>0.507</td>
<td>tINS</td>
<td>RR</td>
<td>9</td>
<td>u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_8_s3/F</td>
</tr>
<tr>
<td>11.066</td>
<td>0.413</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_8_s1/CE</td>
</tr>
</table>
<b>Data Required Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>AHB_CLK</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>AHB_CLK_ibuf/I</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tINS</td>
<td>RR</td>
<td>4323</td>
<td>AHB_CLK_ibuf/O</td>
</tr>
<tr>
<td>10.413</td>
<td>0.413</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_8_s1/CLK</td>
</tr>
<tr>
<td>10.101</td>
<td>-0.311</td>
<td>tSu</td>
<td> </td>
<td>1</td>
<td>u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_8_s1</td>
</tr>
</table>
<b>Path Statistics:</b>
<table class="summary_table">
<tr>
<td class="label">Clock Skew:</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship:</td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level:</td>
<td>12</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay:</td><td> cell: 0.000, 0.000%; route: 0.413, 100.000%</td></tr>
<tr>
<td class="label">Arrival Data Path Delay:</td><td> cell: 5.734, 53.819%; route: 4.537, 42.591%; tC2Q: 0.382, 3.590%</td></tr>
<tr>
<td class="label">Required Clock Path Delay:</td><td> cell: 0.000, 0.000%; route: 0.413, 100.000%</td></tr>
</table>
<br/>
<h3>Path&nbsp4</h3>
<b>Path Summary:</b></br>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-0.965</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>11.066</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.101</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_cs_r_1_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_7_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>AHB_CLK[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>AHB_CLK[R]</td>
</tr>
</table>
<b>Data Arrival Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>AHB_CLK</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>AHB_CLK_ibuf/I</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tINS</td>
<td>RR</td>
<td>4323</td>
<td>AHB_CLK_ibuf/O</td>
</tr>
<tr>
<td>0.413</td>
<td>0.413</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_cs_r_1_s0/CLK</td>
</tr>
<tr>
<td>0.795</td>
<td>0.382</td>
<td>tC2Q</td>
<td>RR</td>
<td>27</td>
<td>u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_cs_r_1_s0/Q</td>
</tr>
<tr>
<td>1.207</td>
<td>0.413</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/master_clk_en_s5/I0</td>
</tr>
<tr>
<td>1.786</td>
<td>0.579</td>
<td>tINS</td>
<td>RR</td>
<td>5</td>
<td>u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/master_clk_en_s5/F</td>
</tr>
<tr>
<td>2.199</td>
<td>0.413</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/spi_ns_1_s18/I0</td>
</tr>
<tr>
<td>2.778</td>
<td>0.579</td>
<td>tINS</td>
<td>RR</td>
<td>3</td>
<td>u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/spi_ns_1_s18/F</td>
</tr>
<tr>
<td>3.190</td>
<td>0.413</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/spi_ns_1_s10/I1</td>
</tr>
<tr>
<td>3.758</td>
<td>0.567</td>
<td>tINS</td>
<td>RR</td>
<td>4</td>
<td>u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/spi_ns_1_s10/F</td>
</tr>
<tr>
<td>4.170</td>
<td>0.413</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/n332_s1/I2</td>
</tr>
<tr>
<td>4.678</td>
<td>0.507</td>
<td>tINS</td>
<td>RR</td>
<td>14</td>
<td>u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/n332_s1/F</td>
</tr>
<tr>
<td>5.090</td>
<td>0.413</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_0_s3/I0</td>
</tr>
<tr>
<td>5.669</td>
<td>0.579</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_0_s3/F</td>
</tr>
<tr>
<td>6.081</td>
<td>0.413</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_0_s2/I0</td>
</tr>
<tr>
<td>6.660</td>
<td>0.579</td>
<td>tINS</td>
<td>RR</td>
<td>6</td>
<td>u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_0_s2/F</td>
</tr>
<tr>
<td>7.073</td>
<td>0.413</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n9_s0/I1</td>
</tr>
<tr>
<td>7.673</td>
<td>0.600</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n9_s0/COUT</td>
</tr>
<tr>
<td>7.673</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n10_s0/CIN</td>
</tr>
<tr>
<td>7.723</td>
<td>0.050</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n10_s0/COUT</td>
</tr>
<tr>
<td>7.723</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n11_s0/CIN</td>
</tr>
<tr>
<td>7.773</td>
<td>0.050</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n11_s0/COUT</td>
</tr>
<tr>
<td>7.773</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n12_s0/CIN</td>
</tr>
<tr>
<td>7.823</td>
<td>0.050</td>
<td>tINS</td>
<td>RR</td>
<td>7</td>
<td>u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n12_s0/COUT</td>
</tr>
<tr>
<td>8.235</td>
<td>0.413</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/tx_bit_cnt_r_4_s6/I0</td>
</tr>
<tr>
<td>8.814</td>
<td>0.579</td>
<td>tINS</td>
<td>RR</td>
<td>8</td>
<td>u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/tx_bit_cnt_r_4_s6/F</td>
</tr>
<tr>
<td>9.226</td>
<td>0.413</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_8_s5/I2</td>
</tr>
<tr>
<td>9.734</td>
<td>0.507</td>
<td>tINS</td>
<td>RR</td>
<td>9</td>
<td>u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_8_s5/F</td>
</tr>
<tr>
<td>10.146</td>
<td>0.413</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_8_s3/I2</td>
</tr>
<tr>
<td>10.654</td>
<td>0.507</td>
<td>tINS</td>
<td>RR</td>
<td>9</td>
<td>u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_8_s3/F</td>
</tr>
<tr>
<td>11.066</td>
<td>0.413</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_7_s1/CE</td>
</tr>
</table>
<b>Data Required Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>AHB_CLK</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>AHB_CLK_ibuf/I</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tINS</td>
<td>RR</td>
<td>4323</td>
<td>AHB_CLK_ibuf/O</td>
</tr>
<tr>
<td>10.413</td>
<td>0.413</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_7_s1/CLK</td>
</tr>
<tr>
<td>10.101</td>
<td>-0.311</td>
<td>tSu</td>
<td> </td>
<td>1</td>
<td>u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_7_s1</td>
</tr>
</table>
<b>Path Statistics:</b>
<table class="summary_table">
<tr>
<td class="label">Clock Skew:</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship:</td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level:</td>
<td>12</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay:</td><td> cell: 0.000, 0.000%; route: 0.413, 100.000%</td></tr>
<tr>
<td class="label">Arrival Data Path Delay:</td><td> cell: 5.734, 53.819%; route: 4.537, 42.591%; tC2Q: 0.382, 3.590%</td></tr>
<tr>
<td class="label">Required Clock Path Delay:</td><td> cell: 0.000, 0.000%; route: 0.413, 100.000%</td></tr>
</table>
<br/>
<h3>Path&nbsp5</h3>
<b>Path Summary:</b></br>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-0.965</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>11.066</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.101</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_cs_r_1_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_6_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>AHB_CLK[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>AHB_CLK[R]</td>
</tr>
</table>
<b>Data Arrival Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>AHB_CLK</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>AHB_CLK_ibuf/I</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tINS</td>
<td>RR</td>
<td>4323</td>
<td>AHB_CLK_ibuf/O</td>
</tr>
<tr>
<td>0.413</td>
<td>0.413</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_cs_r_1_s0/CLK</td>
</tr>
<tr>
<td>0.795</td>
<td>0.382</td>
<td>tC2Q</td>
<td>RR</td>
<td>27</td>
<td>u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_cs_r_1_s0/Q</td>
</tr>
<tr>
<td>1.207</td>
<td>0.413</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/master_clk_en_s5/I0</td>
</tr>
<tr>
<td>1.786</td>
<td>0.579</td>
<td>tINS</td>
<td>RR</td>
<td>5</td>
<td>u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/master_clk_en_s5/F</td>
</tr>
<tr>
<td>2.199</td>
<td>0.413</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/spi_ns_1_s18/I0</td>
</tr>
<tr>
<td>2.778</td>
<td>0.579</td>
<td>tINS</td>
<td>RR</td>
<td>3</td>
<td>u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/spi_ns_1_s18/F</td>
</tr>
<tr>
<td>3.190</td>
<td>0.413</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/spi_ns_1_s10/I1</td>
</tr>
<tr>
<td>3.758</td>
<td>0.567</td>
<td>tINS</td>
<td>RR</td>
<td>4</td>
<td>u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/spi_ns_1_s10/F</td>
</tr>
<tr>
<td>4.170</td>
<td>0.413</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/n332_s1/I2</td>
</tr>
<tr>
<td>4.678</td>
<td>0.507</td>
<td>tINS</td>
<td>RR</td>
<td>14</td>
<td>u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/n332_s1/F</td>
</tr>
<tr>
<td>5.090</td>
<td>0.413</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_0_s3/I0</td>
</tr>
<tr>
<td>5.669</td>
<td>0.579</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_0_s3/F</td>
</tr>
<tr>
<td>6.081</td>
<td>0.413</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_0_s2/I0</td>
</tr>
<tr>
<td>6.660</td>
<td>0.579</td>
<td>tINS</td>
<td>RR</td>
<td>6</td>
<td>u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_0_s2/F</td>
</tr>
<tr>
<td>7.073</td>
<td>0.413</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n9_s0/I1</td>
</tr>
<tr>
<td>7.673</td>
<td>0.600</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n9_s0/COUT</td>
</tr>
<tr>
<td>7.673</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n10_s0/CIN</td>
</tr>
<tr>
<td>7.723</td>
<td>0.050</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n10_s0/COUT</td>
</tr>
<tr>
<td>7.723</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n11_s0/CIN</td>
</tr>
<tr>
<td>7.773</td>
<td>0.050</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n11_s0/COUT</td>
</tr>
<tr>
<td>7.773</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n12_s0/CIN</td>
</tr>
<tr>
<td>7.823</td>
<td>0.050</td>
<td>tINS</td>
<td>RR</td>
<td>7</td>
<td>u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n12_s0/COUT</td>
</tr>
<tr>
<td>8.235</td>
<td>0.413</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/tx_bit_cnt_r_4_s6/I0</td>
</tr>
<tr>
<td>8.814</td>
<td>0.579</td>
<td>tINS</td>
<td>RR</td>
<td>8</td>
<td>u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/tx_bit_cnt_r_4_s6/F</td>
</tr>
<tr>
<td>9.226</td>
<td>0.413</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_8_s5/I2</td>
</tr>
<tr>
<td>9.734</td>
<td>0.507</td>
<td>tINS</td>
<td>RR</td>
<td>9</td>
<td>u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_8_s5/F</td>
</tr>
<tr>
<td>10.146</td>
<td>0.413</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_8_s3/I2</td>
</tr>
<tr>
<td>10.654</td>
<td>0.507</td>
<td>tINS</td>
<td>RR</td>
<td>9</td>
<td>u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_8_s3/F</td>
</tr>
<tr>
<td>11.066</td>
<td>0.413</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_6_s1/CE</td>
</tr>
</table>
<b>Data Required Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>AHB_CLK</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>AHB_CLK_ibuf/I</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tINS</td>
<td>RR</td>
<td>4323</td>
<td>AHB_CLK_ibuf/O</td>
</tr>
<tr>
<td>10.413</td>
<td>0.413</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_6_s1/CLK</td>
</tr>
<tr>
<td>10.101</td>
<td>-0.311</td>
<td>tSu</td>
<td> </td>
<td>1</td>
<td>u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_6_s1</td>
</tr>
</table>
<b>Path Statistics:</b>
<table class="summary_table">
<tr>
<td class="label">Clock Skew:</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship:</td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level:</td>
<td>12</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay:</td><td> cell: 0.000, 0.000%; route: 0.413, 100.000%</td></tr>
<tr>
<td class="label">Arrival Data Path Delay:</td><td> cell: 5.734, 53.819%; route: 4.537, 42.591%; tC2Q: 0.382, 3.590%</td></tr>
<tr>
<td class="label">Required Clock Path Delay:</td><td> cell: 0.000, 0.000%; route: 0.413, 100.000%</td></tr>
</table>
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